1. Field of Industrial Application
The present invention relates to a semiconductor integration circuit apparatus and a method for making the same and, more particularly, to stacked capacitor cells constructing a dynamic random access memory (hereinafter referred to as DRAM) and a method for making such cells.
2. Prior Art
FIG. 24 shows a cross-sectional view of a prior art stacked capacitor cell for forming a DRAM. In FIG. 24, a reference number 1 indicates a semiconductor substrate, 2 indicates a field oxide film, 3 indicates a source region, 4 indicates a drain region, 5 indicates a gate electrode and word line, 6 indicates a bit line, 7 indicates an inter-layer insulating film, 8 indicates an electric charge storage electrode, 9 indicates a capacitor insulation film, and 10 indicates a plate electrode. Furthermore, 13a indicates an upper insulating film and 15 indicates a side wall of an oxide film. The semiconductor substrate 1 is divided into a plurality of memory cells by the field oxide film 2. A MOS transistor for the memory cell comprises the source region 3, the drain gate 4, a gate oxide film 11a and the gate electrode 5 formed on the surface of the semiconductor substrate 1. The capacitor cell for the memory cell comprises the electric charge storage electrode 8, the capacitor insulation film 9 and the plate electrode 10. The electric charge is stored in the electric charge storage electrode 8. When a voltage is applied to the gate electrode 5, the MOS transistor turns on, and the electric charge stored in the electric charge storage electrode 8 flows to the bit line 6 through the source region 3 in order to write and/or read information.
According to the prior art stacked capacitor cell, as the DRAM becomes large in memory capacitance while each element constructing the DRAM is reduced in size, a problem arises that the decrease in area of the memory cell results in insufficient electric charge amount.
Further, various memory cells having three-dimensional structures have been proposed to increase the capacitance of the cell. However, the minimum scale of such a three-dimensional structure is limited to a resolution of the photolithography and, accordingly, it is difficult to realize a complex configuration by the photolithographic technique. In order to realize such a complex configuration, it becomes necessary to increase the height of the capacitor. However, in this case, the height difference between the memory cell portion and the circumferential circuit portion becomes large resulting in difficulty in patterning the wiring to be formed on said height difference, and breaking of the wiring.